[Generale] REMINDER SEMINARIO - SYSTEM SOFTWARE CHALLANGES IN THE EXASCALE ERA - DR. R. GIOIOSA

[Roberto Giorgi]

Carissimi,
vi ricordo che domani 16 SETTEMBRE si svolgera' il seminario del Dr. Gioiosa.

Roberto.


DOVEQUANDO
------------------------
Via Roma 56, Siena  - Edificio S. Niccolo', Aula 145 - 16 SETTEMBRE
2011 - ore 10:00

TITOLO
-----------
System software challanges in the exascale era

ABSTRACT
-----------------
High performance computing systems have shown an impressive growth so
far with a performance increase of 10x every 3.6 years. Performance
predictions seem to confirm this trend for the future and exascale
performance are expected by 2018. Meeting this deadline respecting
cost budgets, however, requires new hardware and software technologies
to solve old and new challenges. Four major challenges have been
identified: Power and Efficiency, Concurrency and Locality,
Reliability, and Storage.

In this talk, I will examine some of these challenges and possible
solutions from a system software prospective. I will show how
performance efficiency can be improved by effectively partitioning
hardware resources for parallel applications that suffer from load
balancing. Through resource partitioning it is possible to control the
tasks speed, reducing the imbalance in parallel applications
transparently to the user and, hence, reducing the total execution
time. We thus implemented a dynamic process scheduler for the Linux
kernel (HPCSched) that automatically and transparently balances HPC
applications according to their run time behavior. Our results show
that our proposal leads to a consistent performance improvement for
NAS benchmarks and for real HPC applications.

In the second part of the talk we will examine the effect of TLB
pressure on parallel applications. Several OSes (CNK, Catamount) for
supercomputers statically fix page table entries into TLB entries.
While this provides minimal performance degradation, it also limits
system flexibility and adaptability to configurations and requirements
that may arise with future applications. Our results on a
state-of-the-art BlueGene/P cluster, show that, to the contrary of
common knowledge, TLB miss overhead is minimal HPC applications if the
page size is in the order of 1MB.

Finally, I will briefly discuss the applicability and limitations of
some checkpoint/restart techniques for future supercomputers as well
as programmability issues caused by the high level of concurrency and
the reduced amount of memory per core.

SPEAKER
-------------------
Roberto Gioiosa: Barcelona Supercomputing Center,
roberto.gioiosa a bsc.es, http://www.sprg.uniroma2.it/home/gioiosa

Dr. Gioiosa is a research scientist at Barcelona Supercomputing Center
(BSC) in the Computer Architecture / Operating System interaction
group since September 2009.
Roberto received his Ph.D. on "High performance computing clusters"
from the University of Rome "Tor Vergata" in 2006. Prior to coming to
BSC, he was graduate student at Los Alamos National Laboratory (LANL)
from April 2004 to June 2005, working on High Performance Computing
(fault tolerance and performance analysis) in the context of the PERCS
project. Roberto started at BSC as post-doc in 2006; at BSC he worked
on operating systems for High Performance Computing Clusters and
optimization for future processor architectures. From September 2008
to September 2009 he was post-doc at IBM TJ Watson Research center, in
the BlueGene group, where he worked on the operating system for next
generation of supercomputers (mainly CNK).
In Fall '09/Winter '10, Roberto visited Prof. Michael L. Scott at the
University of Rochester (NY). During his visit, Roberto worked on
characterization of resilient memory usage and GPU scheduling for
multimedia applications.

Since 2006 Roberto has also been an external collaborator of the
System Programming Research Group at the University of Rome "Tor
Vergata".


--
********************************************
PLEASE NOTE THE NEW PHONE NUMBERS
-------------------------------
Roberto Giorgi, PhD
Dipartim. Ing. Informazione, Via Roma 56 c/o INGEGNERIA, 53100 Siena (Italy)
http://www.dii.unisi.it/~giorgi
tel: +39-0577-191-5182 OR +39-0577-23-4850,,,,1019
fax: +39-0577-191-9064
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